The present invention relates generally to a semiconductor chip, and more specifically to a command decoder and a semiconductor memory device including the same.
A semiconductor memory device is used for storing data in electronic tools such as a computer and a communication apparatus. The semiconductor memory device can be classified, for example, as a dynamic random access memory (DRAM), a synchronous random access memory (SRAM), a flash memory, and a read only memory (ROM), among others. DRAM is the most common type of semiconductor memory device.
The semiconductor memory device receives data from a memory controller and stores the data or transmits the stored data to the memory controller. Data is exchanged between the memory controller and the semiconductor memory device by generally using one of two methods, depending on the type of data path used.
According to the first method, as shown in FIG. 1, a memory controller 1 and first and second semiconductor memory devices 2 and 3 exchange data by using a common transmission line DQLINE1. In an integrated circuit with such a structure, while the first semiconductor memory device 2 outputs data, the second semiconductor memory device 3 disables a data input buffer since data read from the first semiconductor memory device 2 is not meant for the second semiconductor memory device 3. This is because the first semiconductor memory device 2 and the second semiconductor memory device 3 transmit data to the memory controller 1 through the common transmission line DQLINE1.
According to the second method, as shown in FIG. 2, a memory controller 4 and first and second semiconductor memory devices 5 and 6 exchange data by using individual transmission lines DQLINE2 and DQLINE3. In the integrated circuit with such a structure, since the first semiconductor memory device 5 and the second semiconductor memory device 6 use the individual transmission lines DQLINE2 and DQLINE3, although the first semiconductor memory device 5 outputs data, the second semiconductor memory device 6 does not need to disable a data input buffer. However, the integrated circuit with the structure as shown in FIG. 2 is designed to perform operations substantially identical to those of the integrated circuit as shown in FIG. 1. That is, in the integrated circuit as shown in FIG. 2, while the first semiconductor memory device 5 outputs data, the second semiconductor memory device 6 disables the data input buffer although the data output by the first semiconductor memory device does not interfere with operation of the second semiconductor memory device 6.